Method and apparatus for generating timing pulses with varying distances

ABSTRACT

A timing pulse generator producing periodic pulse sequences with the distances between successive pulses in each sequence varying according to a periodically varying voltage employed as the upper voltage limit to which a charging capacitor is charged. A bistable switch is responsive to the charging capacitor reaching the upper voltage limit to effect both a change in level in its output voltage and discharge of the capacitor to a lower voltage limit. Upon the charging capacitor reaching the lower voltage limit the bistable switch is again responsive to effect both a change in level in its output voltage back to its original level and the charging of the capacitor.

[ 11 3,745,367 [451 Jul 10, 1973 METHOD AND APPARATUS FOR GENERATINGTIMING PULSES WITH VARYING DISTANCES [75] Inventors: Hans R. Schindler,Au; Peter Vettiger, Thalwil, both of Switzerland [73] Assignee:International Business Machines Corporation, Armonk, NY.

[22] Filed: May 2, 1972 [21] Appl. No.: 249,581

[52] US. Cl. 307/108, 328/63 [51] Int. Cl. H03k 3/00 [58] Field ofSearch 307/108, 107, 106; 378/59, 63, 66, 67

[56] References Cited UNlTED STATES PATENTS 3,587,065 6/197l Kuntze307/108 Primary Examiner-Herman J. Hohauser Attorney-John A. Jordan etal.

[5 7] ABSTRACT A timing pulse generator producing periodic pulsesequences with the distances between successive pulses in each sequencevarying according to a periodically varying voltage employed as theupper voltage limit to which a charging capacitor is charged. A bistableswitch is responsive to the charging capacitor reaching the uppervoltage limit to effect both a change in level in its output voltage anddischarge of the capacitor to a lower voltage limit. Upon the chargingcapacitor reaching the lower voltage limit the bistable switch is againresponsive to effect both a change in level in its output voltage backto its original level and the charging of the capacitor.

13 Claims, 8 Drawing Figures 52 v j I) T Q 1 E I 12 17 l l 83 [V2 I l 86I V5 o- 0 CLOCK L J' L311 PATENIED JUL 1 0 I373 SHEEI 2 0f 3 FIG. 4

CLOCK PAIENIEU JUL I 0 ms SHEET 3 OF 3 FIG. 7

OUTPUT LIMITER INPUT FEEDBACK NETWORK CLOCK FIG. 8

DIGITAL OUT SEQUENCE ANALYZER AUDIO IN TIMING PULSE GENERATOR CLOCKMETHOD AND APPARATUS FOR GENERATING TIMING PULSES WITH VARYING DISTANCESBACKGROUND OF THE INVENTION The present invention relates to timingpulse generation and, more particularly, to a method and apparatus forgenerating timing pulses whose distances from preceeding or succeedingtiming pulses, respectively, vary with time.

Timing pulse generators, of the type above mentioned, have particularuse in digital applications, where measured values should be indicateddigitally, as for instance in digital measuring of noise levels with anindication in decibel, or of light (luxmeter), and in digital tubevoltmeters. A further field of application is in logarithmicanalog/digital conversion, which is utilized, for example, in digitalspeech-coding and video techniques. In contrast to timing pulsegeneration for chronometry, for example, where the best possibleconstancy of the distance between neighboring timing pulses over verylong periods of time is the objective, it is the controlled variabilityof the interpulse distances which is desirable for the applicationshereinabove mentioned, this variability of course, in most cases havingto follow a certain periodicity.

Conventional techniques for generating timing pulses with varyingdistances between the pulses typically rely on circuits in which thenon-linearity of a diode characteristic is used. However, most of thesecircuits have the disadvantage of drifting with temperature, since thediodes are extraordinarily temperature-dependent. It has been undertakento overcome this disadvantage by placing the timing pulse generators inthermostatically controlled ovens. It is clear, however, thatconsiderable apparatus is required for such an arrangement.

It is, therefore, an object of the present invention to provide a newmethod and apparatus for the generation of timing pulse sequences, whichpulse sequences exhibit periodically varying distances between therespective pulses over the sequences.

It is a further object of the present invention to provide a timingpulse generator for generating pulses with periodically varyingdistances therebetween, which generator is greatly independent oftemperature variations and which permits the realization of distancesbetween succeeding timing pulses in accordance with optional,predetermined mathematical laws, and with moderate expenditure incircuitry.

The method and apparatus according to the principles of the presentinvention simply employ the value of energy stored in an energyreservoir whereby the energy is compared to two different referencevalues and the results of the comparison are supplied to a bistablecircuit which switches states when the value of energy matches and/orsurpasses one of the reference values. The output signal of the bistablecircuit, which is indicative of its switching state, is utilized forcontrolling at least one source of energy connected to the energyreservoir.

More particularly, the time pulse generator according to the presentinvention is characterized by an energy reservoir and at least onesource of energy connectable to the energy reservoir. In addition, twocomparators are employed for comparing the value of the energy stored inthe energy reservoir to two different reference values individuallyappertaining to the comparators. A bistable circuit responsive to thecomparator outputs, is coupled to the timing pulse output and to thecontrol input of a switch associated with the source of energy wherebyrespective timing pulses and control signals are produced in accordancewith changes in the state of said bistable circuit.

The foregoing and other objects, features and advantages of theinvention will be apparent from the following more particulardescription of the preferred embodiments of the invention as illustratedin the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 through 3 show various formsof one of the reference voltages, and the relationship of the timingpulse sequence thereto.

FIG. 4 is a basic circuit diagram of the timing pulse generator inaccordance with the present invention.

FIG. 5 shows unsymmetrical charging and discharging currents and theassociated timing pulse sequence.

FIG. 6 is a circuit diagram of an exponential timing pulse generator.

FIG. 7 is a schematic diagram of a deltacoder.

FIG. 8 is a block-diagram of a deltacoder.

DETAILED DESCRIPTION OF THE DRAWINGS The principles of the method andapparatus according to the present invention are based upon comparisonof the energy stored in an energy reservoir (for instance, a capacitor)to two different reference values, and the switching of the energysupplied to the energy reservoir in dependence upon the result of thecomparison. For this purpose, the first one of the reference values isdefined as the lower threshold and the second reference value as theupper threshold. If energy is continuously supplied to-the energyreservoir, its value will eventually reach the upper threshold and causea polarity reversal of the source of energy, whereby the energyreservoir commences to discharge until the lower threshold is reached(and possibly surpassed) whereupon the charging commences again.

In this way, the energy value pendulates continuously back and forthbetween the two thresholds. In the case where a capacitor is employed asthe energy reservoir and two constant reference voltages are employed,the voltage at the terminals of. the capacitor would have essentially atriangular form with the bases of succeeding triangles having equallengths (the triangles would be' congruent). I

It is an important aspect of the present invention that only one of thereference values is constant while the other varies as a function oftime. Assuming that the second referencevalue is, for instance, avoltage that rises linearly with time (sawtooth voltage), the voltage atthe terminals of the capacitor will again have triangular form, but thelengths of the bases of succeeding triangles will increase, by a fixedpercentage (with respect to the preceeding base length), since theheights of the triangles become greater and greater due to thecontinuously rising upper threshold. The triangles are, therefore, nolonger congruent as was the case with two constant reference values, butonly similar. The length of the bases of succeeding triangles form ageometrical sequence, and the increase of the distances betweenreference points of succeeding triangles is exponential with respect totime.

As previously stated, the result of the comparison operation is suppliedto a bistable circuit which generates a constant dc output signal foreach of its switching states, and which, once it occupies a switchingstate retains same until the opposite threshold is reached. For mostapplications, the pattern generated by the timing pulse generator mustbe repeated periodically. It is obvious that the period of theinternally generated sampling interval may be used for this purpose,particularly where the application is in analog/digital conversion, orthe like. Of course, an external frequency source may also be employed.

FIG. 1 shows a sawtooth envelope curve V the form of the associatedpotential at the terminals of the capacitor V, and the output signal ofthe timing pulse generator E. FIGS. 2 and 3 show examples of nonlinearenvelope curves and their associated terminal potential and outputsignals. In all cases, the increase of the distances between adjacentoutput signals is clearly visible. As can be seen, in FIG. 2 theincrease occurs only towards the end of the cycle. On the other hand, inFIG. 3, which depicts a RC charging operation there is initially a rapidincrease according to an exponential function, with growingstabilization of the intervals towards the end of each cycle. The timingpulse generator of the present invention can be adapted to almost anyapplicationv (as far as the increase or decrease of the distance betweenthe pulses is concerned) by means of suitably distorting the sawtoothvoltage by a non-linear circuit.

FIG. 4 shows a basic circuit diagram of the timing pulse generatoraccording to the present invention. Basically, the circuitry shown is aspecial multivibrator which is distinguished over many others by the useof only one capacitor. Capacitively coupled multivibrators generallyhave two capacitors which cause the specific disadvantage that thesemultivibrators, under certain circumstances, do not spontaneously startoscillating. They must, therefore, receive an initial external triggerpulse. With a single capacitor, as in the present case, themultivibrator cannot but start oscillating immediately under allstarting conditions.

Connected to capacitor C, are two energy sources 1 1 and 12 which supplythe currents 21 and I, respectively. The direction of current flow isdefined such that the current I flows continuously out of the capacitorC,, while the current 2I flows into the capacitor C, whenever the switchS, is closed, such that the resulting current is H or I, depending uponthe position of the switch 8,.

The currents of current sources 11 and 12 need not necessarily obey therelation 2:1. They may, for example, supply currents of equal magnitude,requiring both current sources to be switched. They may also haveunsymmetrical magnitude resulting in different leading and trailingedges of the charging and discharging currents, respectively. Thecharging and discharging, respectively, of the capacitor C, isterminated whenever the potential of the capacitor reaches an upper orlower threshold. These thresholds are represented by reference voltageswith which the potential on capacitor C, is continuously compared. Inthe embodiment of the invention to be described, the lower threshold isdefined as zero volts. The other (upper threshold) corresponds to theinstantaneous value of a periodically varying voltage V, (t). Assuggested above, this voltage V may be a sawtooth voltage generated, forexample, by a sawtooth generator comprising a current source 13supplying the current I, and a capacitor C operating in conjunction witha reset mechanism.

A comparison of the voltage on capacitor C, to the reference voltages isperformed by two comparators 14 and 15. These comparators each have twoinput terminals, which in FIG. 4 are designated and respectively. Theinput of comparator l4 and the input of comparator 15 are connected tocapacitor C,, while the two other inputs of the comparators are suppliedwith the respective reference voltages. The output terminals ofcomparators 14 and 15 are coupled to a bistable circuit (belowdesignated storage cell 16) consisting of two NAND-gates l7 and 18. Eachof the NAND-gates has two input terminals, with one of the two inputterminals for each gate connected to the respective output terminal ofthe associated comparators 14 and 15. The second input terminal of eachNAND- gate is coupled to the output of the other.

The comparators 14 and 15 in FIG. 4 are designated such that they supplya negative output signal (taken hereinafter as logic level zero)whenever their respective threshold level is reached or surpassed. Sincethe comparators are working against each other, they neversimultaneously supply a negative output signal to the respective inputsA and D of NAND-gates l7 and 18. The NAND-gates l7 and 18 have thefollowing truth tables, with the letters A through D designating theinputs, as shown in FIG. 4: Truth Table 1 Truth Table 2 NAND-Gate l7NAND-Gate 18 A C C D B 0 0 l 0 0 l l 0 l l 0 l O l l O l l l l 0 l l 0Under the assumed condition that comparator 15 produces an output signalcorresponding to logic level zero (A=0), when its associated thresholdhas been reached or passed, then, conversely, at such time comparator 14necessarily supplies an output signal corresponding to'logic level one(D=l It follows from Truth Table 1 that if A=0, then C=l is always true.From Truth Table 2 it can be seen that with C=l and -D=l output B ofNAND-gate 18 must supply the signal 0, and this, it can further be seen,is consistent with the condition stated in the first line of Truth Table1.

Because of the switching characteristics of the comparators, the abovedescribed state is preserved until the O-volt threshold of thecomparator 14 is actually reached. When this occurs, comparator 14supplies a negative signal (logic level zero) to the D-input ofNAND-gate l8 (D=0). This forces the output B of NAND-gate 18 to go tologic level one (B=l Table 2). With A=l, output C of NAND-gate 17changes to logic level zero (C=0, Table 1). Meanwhile, the signal atinput D of NAND-gate 18 has disappeared (D=l It follows from Truth Table2 that B remains B=l and from Truth Table 1, that C is C=0. This is, inturn, consistent with Truth Table 2.

The output signal B of NAND-gate l8 occurring at point 19 (cf. E in FIG.1 to 3) is used to operate the switch 5,, which controls the chargingand discharging respectively, of the capacitor C, via current sources 11and 12. As mentioned previously, capacitor C, is discharged with thecurrent I when switch S, is in its open position and is charged with thecurrent 2II=+-I when switch S, is in its closed position.

In all cases in which the reference voltage V, must be brought back toan initial value, be it periodically or aperiodically, it is importantto note that this initial value should not be zero volts, since then thetransitions between charging and discharging of the capacitor C, wouldoccur with infinitely high frequency which, of course, is undesirable.In FIG. 4, a pair of switches S and S are shown by which the dischargingof capacitor C,(V,= volt) and the resetting of the reference voltage Vto its initial value may be performed. The switches S and 8;, may beoperated, for example, with the clock frequency of the samplingfrequency. In the case where the timing pulse generator of the presentinvention is used for speech coding, utilization of the 64 kHz samplingfrequency is effective. While the capacitor C, is completely dischargedat the end of each sampling interval (switch S short-circuits thecapacitor), the voltage V is lowered only to the bias voltage V appliedto the switch S The bias voltage V may be 5 to percent of the maximumamplitude of the reference voltage V for example.

In case the charging and discharging currents of the capacitor are ofequal magnitude, the voltage at the terminals of the capacitor assume atriangular form with all triangles being similar since their heights andbase lengths have always the same mutual relation. A triangle with apeak voltage V, corresponds, then, to a complete inpulse of the outputsignal at point 19. Since the triangles are all isosceles, the top andgap of any one pulse will have equal lengths.

This is not the case where the charging currents have unequal magnitude(1,, 9 1,). With unequal magnitude charging currents, the triangles ofthe capacitor voltage are no longer isosceles, such that top and gap ofthe individual pulses are of the same length. An example of a case wherethe charging current is greater than the discharging current is shown inFIG. 5.

The mathematical law defining the function by which the distance betweensucceeding pulses increase or decrease over a cycle is determined by theform of the reference voltage V An exponential increase is obtained, asmentioned above, for (periodically) linearly increasing referencevoltages. Other non-linear laws may be obtained by suitably distortingthe wave shape, via introducing a non-linear circuit 20, as shown inFIG. 4. Such non-linear circuit may comprise,'for example, a fieldeffect transistor (with quadratic characteristic), a diode (withexponential or logarithmic characteristic), or other active or passiveelements or combinations thereof.

FIG. 6 shows a simplified circuit diagram arrangement of a timing pulsegenerator with exponential increase .of the distances between succeedingpulses, which arrangement permits the execution of the method accordingto the present invention. The current source 1 1 of FIG. 4 is shown inFIG .'6 to comprise a pnp transistor 43 and a resistor 32. The currentsource 12 of FIG. 4 is shown in FIG. 6 to comprise an npn transistor 33and a resistor 34. For the embodiment shown, the relationship betweenthe currents is 2:1 in favor of current source 11. The comparators l4and 15 of FIG. 4 are shown in FIG. 6 comprising pairs of transistors35-36 and 37-38, respectively. The storage cell 16 of FIG. 4 comprisestransistors 39 and 40 in FIG. 6. Since the mode of operation of thelatter is not self-evident it will presently be explained briefly.

When the voltage V, on capacitor C, assumes values above zero volts, thetransistor 35 is conducting. With the voltage V, approaching zero volts,the transistor 36 grows more and more conductive until, at zero volts,the current is equally distributed between transistors 35 and 36. Forvalues below zero volts, the current is shifted more and more into theright branch, which means that the transistor 36 is more conductive thanthe transistor 35. Since the collector current of transistor 36 flowsthrough resistors 41 and 42, when this current becomes sufficient thevoltage drop across these resistors causes the base of transistor 39 tobecome sufficiently negative so that transistor 39 is cut off.Therefore, the current is shifted over to the right branch of lattertransistor pair 39-40, whereby transistor 40 starts conducting. As aresult, the voltage drop across resistor 42 increases such that thevoltage on the base of transistor 39 drops further.

At the same time that transistor 40 of FIG. 6 becomes conductive, thevoltage on the base of transistor 43 drops causing the same to alsobecome conductive, whereby the condition of FIG. 4 wherein switch S, isclosed and capacitor C, becomes charged, is obtained. Meanwhile, storagecell 16 maintains its state. The voltage V, increases until comparator15 responds. As soon as the voltage V, becomes more positive than V thecurrent through transistor 37 starts flowing and the flow of currentthrough transistor 38 decreases until it finally disappears entirely.This causes the storage cell 16 to become currentless since the commonemitter line 44 of transistors 39 and 40 is connected to the col lectorof transistor 38.

The current drawn by storage cell 16 was, prior to this currentlesscondition flowing through transistor 40 and had, thus, caused a voltagedrop across resistor 42. The resultant reduction in current flow throughresistor 42 however, creates an increase in potential on line 45 and thebase of transistor 39. When the potential on the base of transistor 39surpasses the fixed potential on the base of transistor 40, transistor39 becomes more conductive than transistor 40 thereby causing thevoltage drop across resistor 42 to further decrease and the base oftransistor 39 to become more positive. The storage cell 16 has, thus,switched to its second stable state Since the potential on capacitor C,at this time is positive, the base of transistor 35 is positive, also,and comparator 14 is thus conducting in its left branch. This means thatcurrentless transistor 36 cannot cause any voltage drop acrossresistors-41 and 42. Because of the increase in potential on line 45,the base of transistor 43 becomes more positive with'respect to the baseof transistor 31. Therefore, transistor 43 is cut off (S, opens) and,accordingly, disconnects the current +2] of capacitor C,. Consequently,capacitor C,, at this time, experiences discharge by the current -I.Likewise, transistor 37 experiences a reduced current flow, since itsbase becomes more negative. From the latter finally follows a shiftingof the current over to the right branch of comparator 15, such thatstorage cell 16 is again supplied the full current. Summarizing, then,it can be seen that the bistable storage cell 16 is switched into onestate through base control, and into the other state through controllingthe entire current flow through the circuit.

The signal of the timing pulse generator of FIG. 6 occurring on line 45(corresponding to point 19 in FIG. 4) may be coupled, as shown, toisolation amplifier 57, which amplifier comprises transistors 46 and 47.The isolation amplifier is provided due to the fact that line 45, whichis used as a control line, is relatively highohmic and can, thereforenot be loaded.

In the arrangement of FIG. 6, the variable reference voltage V is asawtooth voltage generated by charging and discharging a capacitor C bymeans of a current source comprising a transistor 48 and a resistor 49.Connected to this sawtooth generator is a reset circuit controlled byclock pulses supplied to an input terminal 50. The clock pulses areguided through diodes 51 and 52 to the base terminals of transistors 53and 54, which transistors the clock pulses drive into saturation.Transistor 54 connects capacitor C to ground, via line 55, wherebycapacitor C is completely discharged upon the occurrence of each clockpulse.

The collector of transistor 53 is connected to capacitor C via a line56. The emitter of transistor 53 is supplied with a small bias voltageV, whose magnitude may, for example, amount to from 5 to percent of theamplitude of the sawtooth voltage. With each clock pulse, capacitor C,is discharged to this latter bias volt age. By this means, it ispossible to avoid the condition whereby the bistable circuit forming thestorage cell 16 has to initially switch infinitely fast. From afunctional point of view, the sawtooth generator shown comprisingelements 48, 49, C 53 (corresponding to S6 in FIG. 4) supplies a voltagewhich increases linearly from a bias voltage to a maximum value, and isperiodical with the clock frequency (or the sampling frequency).

The timing pulse generator of FIG. 6 may be employed, for example, in anadaptive deltacoder. Deltacoders are frequently used for the coding ofspeech so as to convert the speech signal occurring in analog form to adigital signal, for purposes of transmission. This technique is wellknown to those skilled in the art and, therefore, will not be explainedin detail. The adaptive deltacoder selects its own step size, independence upon the instantaneous value of the analog signal. Thisadaptation is made indirectly by determining what the sequences of thedigital information, generated by the coder, look like. From the lengthsof the sequences, one can conclude whether the step size was chosencorrectly (or is too small or too large) and when incorrect, in whichdirection a possibly necessary change of the step size should be made.However, the adaptation of the step size is not effected upon everyslight deviation, but only if a deviation in one direction remains overa preselectable number of sampling intervals. This deviation manifestsitself in a sequence of invariable binary values. As mentioned before,the maximum, still tolerable length of the sequence can be preselectedand depends upon the admissible coding noise.

Typical simple coder arrangements employ a feedback system in which thefeedback signal is quantized in amplitude and time. Accordingly, pulsesare obtained which are periodic in a fixed sampling interval, with theamplitude quantizing assuming values of +1 and -l. The pulses are summedup, which in the most simple case is done in an integrator, generally ina linear network arrangement. FIG. 7 shows schematically a deltacodercomprising differential amplifier 60, limiter 6], switch 62 and feedbacknetwork 63. This arrangement is the special case of a servo system, withswitch 62 being operated at the sampling frequency.

FIG. 8 shows a block diagram of a deltacoder which makes use of thetiming pulse generator of the present invention. Comparator 71 issupplied with the speech signal, which is fed into input terminal 72.Comparator 71 acts as quantizer when connected, as shown, to flipflop73. Connected to the output of flipflop 73 are sequence analyzer 74, andintegrator network 75. Flipflop 76, which is coupled to diode network77, is provided for determining the absolute value of charge Q flowinginto integrator 75, i.e., for establishing the step size. It is clearthat the charge Q is the product of current and time, with the currentin this circuit being limited, as shown, by limiter diode 78. It shouldbe recognized that it may be possible to use a single limiter diode ifthe other diodes are suitably connected such that the current throughthe limiter diode can always flow in the same direction. Therefore, thecurrent pulses or have always practically the same magnitude.

As shown in FIG. 8, the signal occurring at the output 79 of flipflop 73is coupled to inverter 80. This signal determines the sign of thecurrent flowing into integrator 75. The duration of current flow isdetermined by the interval during which flipflop 76 is in its on state.Whenever flipflop 76 is in its off state, the current flows into ashunt.

Timing pulse generator 81, in accordance with the present invention, isconnected to sequence analyzer 74 as well as to flipflop 76. It iscontrolled by the sampling signal (clock). The digital output signal ofthe deltacoder, appearing at the output of flipflop 73, is continuously(i.e., at clock time) monitored in that the sequence of the binaryvalues 0 and l is checked. A detector contained in sequence analyzer 74counts the identical binary values of a sequence, and causes a counterto be set to a higher or lower value whenever the sequences of identicalbinary value surpass, or fall short of, a predetermined value. Over-andunderflow of the counter is prevented by logic circuitry. The counterkeeps track of the step size (db) in binary form.

It has been found that for a deltacoder having an acceptable dynamicrange, a compression ratio (i.e., ratio of largest to smallest stepsize) of approximately 24 db is appropriate. The difference betweenadjacent step sizes, then, should not exceed 2 db. This means that thecoder must, for example, be able to produce 13 positive and 13 negativesteps of pre-selectable size.

This latter can be achieved by having the timing pulse generator execute25 charging and discharging operations within any one sampling interval,and by using the commencements of the charging operations as timingindications. The intervals obtained in this way grow exponentially withtime.

The step size active at any one instant of time is related to theobserved sequence of identical binary values by means of a comparatorcontained in sequence analyzer 74, and the step size is reduced, held,or increased by using the results of the comparison. As mentionedbefore, the step size corresponds to the charge Q flowing into theintegrator 75, the charge being the product of the constant current Iflowing through limiter diode 78, and the time during which it flows.The time interval of current flow is determined by setting flipflop 76.The output signal of integrator 75 is supplied to comparator 7i, wherebyit is compared to the input speech signal.

What is claimed is:

1. A timing pulse generator for generating pulses having distancestherebetween which vary according to a pre-selected function,comprising:

charge storage means;

means coupled to said charge storage means to charge said charge storagemeans in response to a first control signal and discharge said chargestorage means in response to a second control signal;

compare circuit means coupled to said charge storage means to provide afirst output signal when said charge storage means charges to a firstvoltage level and to provide a second output signal when said chargestorage means discharges to a second voltage level; and

switching circuit means coupling the first and second output signal ofsaid compare circuit means to said means to charge so that the saidfirst output signal of said compare circuit means initiates productionof said second control signal and the said second output signal of saidcompare circuit means initiates production of said first control signal,whereby pulses are generated having distances therebetween which varyaccording to said pre-selected function.

2. The timing pulse generator as set forth in claim 1 wherein said firstvoltage level varies with time.

3. The timing pulse generator as set forth in claim 2 wherein said firstvoltage level varies periodically according to said pre-selectedfunction.

4. The timing pulse generator as set forth in claim 3 wherein saidsecond voltage level is constant.

5. The timing pulse generator as set forth in claim 4 wherein the periodof said pre-selected function is initiated by regularly spaced clockpulses which act to initiate a sampling interval corresponding to saidperiod.

6. The timing pulse generator as set forth in claim 5 wherein switchmeans coupled to said charge storage means are responsive to the saidclock pulses which initiate said sampling interval to discharge saidcharge storage means to said constant voltage level.

7. The timing pulse generator as set forth in claim 6 wherein said firstvoltage level varies periodically according to a sawtooth waveformfunction.

8. A method of generating timing pulses in periodic sequences with thedistance between successive pulses in each sequence varying according toa pre-selected function, comprising the steps of:

causing a capacitor to charge toward a first voltage level in responseto a first control indication produced each time said capacitor reachesa second voltage level and causing said capacitor to discharge towardsaid second voltage level in response to a second control indicationproduced each time said capacitor reaches said first voltage level, withsaid first voltage level periodically varying with time according tosaid function;

comparing the voltage on said capacitor with said first voltage level toproduce a first signal when the voltage on said capacitor charges tosaid first voltage level and comparing the voltage on said capacitorwith said second voltage level to produce a second signal when thevoltage on said capacitor charges to said second voltage level; andproducing said first control indication in response to said secondsignal and said second control indication in response to said firstsignal, whereby said first and second control indications define thepulses in said periodic sequences.

9. The method as set forth in claim 8 wherein said second voltage levelis constant.

10. The method as set forth in claim 9 wherein the period of saidpre-selected function is initiated in accordance with the occurrence ofregularly spaced clock pulses.

11. The method as set forth in claim 10 wherein said first voltage levelperiodically varies to form a sawtooth waveform.

12. The method as set forth in claim 1 1 including the further step ofcausing said capacitor to discharge to said constant voltage level eachtime a clock pulse occurs.

13. A timing pulse generator for generating timing pulses in periodicsequences with the distance between successive pulses in each sequencevarying according to a pre-selected function, comprising:

capacitor charge storage means;

means coupled to said capacitor charge storage means to charge saidcapacitor charge storage means in response to a first control signal andto discharge said capacitor charge storage means in response to a secondcontrol signal;

first and second reference voltage means with the amplitude of thevoltage of said first reference voltage means periodically varying withtime and with the amplitude of the voltage of said second referencevoltage means being constant with time;

compare circuit means coupled to said capacitor charge storage means andto said first and second reference voltage means for comparing thevoltage level on said capacitor charge storage means with the amplitudeof the respective reference voltage: of said first and second referencevoltage means so as to produce a first output signal therefrom when thevoltage levelon said capacitor charge storage means reaches the saidamplitude of the voltage of said first reference voltage means and toproduce a second output signal therefrom when the voltage level on saidcapacitor charge, storage means reaches the said amplitude of thevoltage of said second reference voltage means; and

bistable switching circuit means coupled between said compare circuitmeans and said means to charge said capacitor charge storage means so asto produce the said first control signal in response to the said secondoutput signal from said compare circuit means and to produce the saidsecond control signal in response to the said first output signal fromsaid compare circuit means, whereby said bistable switching circuitmeans acts to produce the said timing pulses in said periodic sequenceswith the distance between successive pulses in each equence varyingaccording to the manner in which said first reference voltage meansperiodically varies with time.

1. A timing pulse generator for generating pulses having distancestherebetween which vary according to a pre-selected function,comprising: charge storage means; means coupled to said charge storagemeans to charge said charge storage means in response to a first controlsignal and discharge said charge storage means in response to a secondcontrol signal; compare circuit means coupled to said charge storagemeans to provide a first output signal when said charge storage meanscharges to a first voltage level and to provide a second output signalwhen said charge storage means discharges to a second voltage level; andswitching circuit means coupling the first and second output signal ofsaid compare circuit means to said means to charge so that the saidfirst output signal of said compare circuit means initiates productionof said second control signal and the said second output signal of saidcompare circuit means initiates production of said first control signal,whereby pulses are generated having distances therebetween which varyaccording to said pre-selected function.
 2. The timing pulse generatoras set forth in claim 1 wherein said first voltage level varies withtime.
 3. The timing pulse generator as set forth in claim 2 wherein saidfirst voltage level varies periodically according to said pre-selectedfunction.
 4. The timing pulse generator as set forth in claim 3 whereinsaid second voltage level is constant.
 5. The timing pulse generator asset forth in claim 4 wherein the period of said pre-selected function isinitiated by regularly spaced clock pulses which act to initiate asampling interval corresponding to said period.
 6. The timing pulsegenerator as set forth in claim 5 wherein switch means coupled to saidcharge storage means are responsive to the said clock pulses whichinitiate said sampling interval to discharge said charge storage meansto said constant voltage level.
 7. The timing pulse generator as setforth in claim 6 wherein said first voltage level varies periodicallyaccording to a sawtooth waveform functIon.
 8. A method of generatingtiming pulses in periodic sequences with the distance between successivepulses in each sequence varying according to a pre-selected function,comprising the steps of: causing a capacitor to charge toward a firstvoltage level in response to a first control indication produced eachtime said capacitor reaches a second voltage level and causing saidcapacitor to discharge toward said second voltage level in response to asecond control indication produced each time said capacitor reaches saidfirst voltage level, with said first voltage level periodically varyingwith time according to said function; comparing the voltage on saidcapacitor with said first voltage level to produce a first signal whenthe voltage on said capacitor charges to said first voltage level andcomparing the voltage on said capacitor with said second voltage levelto produce a second signal when the voltage on said capacitor charges tosaid second voltage level; and producing said first control indicationin response to said second signal and said second control indication inresponse to said first signal, whereby said first and second controlindications define the pulses in said periodic sequences.
 9. The methodas set forth in claim 8 wherein said second voltage level is constant.10. The method as set forth in claim 9 wherein the period of saidpre-selected function is initiated in accordance with the occurrence ofregularly spaced clock pulses.
 11. The method as set forth in claim 10wherein said first voltage level periodically varies to form a sawtoothwaveform.
 12. The method as set forth in claim 11 including the furtherstep of causing said capacitor to discharge to said constant voltagelevel each time a clock pulse occurs.
 13. A timing pulse generator forgenerating timing pulses in periodic sequences with the distance betweensuccessive pulses in each sequence varying according to a pre-selectedfunction, comprising: capacitor charge storage means; means coupled tosaid capacitor charge storage means to charge said capacitor chargestorage means in response to a first control signal and to dischargesaid capacitor charge storage means in response to a second controlsignal; first and second reference voltage means with the amplitude ofthe voltage of said first reference voltage means periodically varyingwith time and with the amplitude of the voltage of said second referencevoltage means being constant with time; compare circuit means coupled tosaid capacitor charge storage means and to said first and secondreference voltage means for comparing the voltage level on saidcapacitor charge storage means with the amplitude of the respectivereference voltages of said first and second reference voltage means soas to produce a first output signal therefrom when the voltage level onsaid capacitor charge storage means reaches the said amplitude of thevoltage of said first reference voltage means and to produce a secondoutput signal therefrom when the voltage level on said capacitor chargestorage means reaches the said amplitude of the voltage of said secondreference voltage means; and bistable switching circuit means coupledbetween said compare circuit means and said means to charge saidcapacitor charge storage means so as to produce the said first controlsignal in response to the said second output signal from said comparecircuit means and to produce the said second control signal in responseto the said first output signal from said compare circuit means, wherebysaid bistable switching circuit means acts to produce the said timingpulses in said periodic sequences with the distance between successivepulses in each sequence varying according to the manner in which saidfirst reference voltage means periodically varies with time.